The present invention relates generally to Built-In Self-Test (BIST) of Integrated Circuits (ICs), Printed Circuit Boards (PCBs), and systems, and more specifically to an apparatus and method for embedding BIST capability within ICs, PCBs, and systems.
Techniques are known that employ scan testing for providing manufacturing test, debug, and programming of electronic circuits. Such scan testing techniques are often performed according to the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture specification (“the IEEE 1149.1 Standard”), which is incorporated herein by reference. The IEEE 1149.1 Standard may also be used to provide In-System Configuration (ISC) of programmable circuits.
The IEEE 1149.1 Standard was initially developed for interconnect testing of PCBs. The IEEE 1149.1 Standard employs a boundary scan path to facilitate access to Input/Output (I/O) pins of devices mounted on a PCB. In addition, the IEEE 1149.1 Standard may be used to access internal scan paths of an IC to facilitate test, debug, ISC, or programming of ICs, PCBs, and systems.
FIG. 1 depicts the conventional IEEE 1149.1 Standard Architecture 100. As shown in FIG. 1, an IC compliant with the IEEE 1149.1 Standard has four (optionally, five) additional component pins TDI, TDO, TCK, and TMS (optionally, TRSTN), which form a Test Access Port (TAP). The IEEE 1149.1 Standard facilitates the connection of TAP ports of multiple electronic circuits to form an IEEE 1149.1 bus, thereby allowing the connected circuits to be accessed using a common TAP protocol. This is typically achieved by connecting the serial data pins TDI and TDO of individual devices in a daisy chain fashion such that the TDO output from a previous device along the chain is connected to the TDI input of a next device in the chain. Then, by connecting all of the TMS and TCK (optionally TRSTN) pins of the devices in common, an overall TAP bus is formed.
FIG. 2 depicts a conventional IEEE 1149.1 bus in a daisy chained configuration 200. As shown in FIG. 2, the TDI pin on a first device U1202.1 and the TDO pin on a last device Un 202.n are used as the serial data input and serial data output of the IEEE 1149.1 bus, respectively. The bus configuration 200 shown in FIG. 2 is typically employed on a single PCB.
FIG. 3 depicts a conventional IEEE 1149.1 bus in a multi-drop configuration 300. When utilized within a system of PCBs, the multi-drop configuration 300 provides for a single TAP bus across a backplane of the system and allows each PCB to make connections to the same set of wires on the multi-drop bus. Because TCK, TMS, TDI and TRSTN are input signals, these signals can be directly connected across the system backplane to each of the TAPs of the individual PCBs. However, signal clashes may result when connecting the multiple TDO outputs onto the single TDO wire of the multi-drop bus. To avoid such signal clashes, the IEEE 1149.1 Standard requires that the TDO output drive out only when serial data is being shifted into or out of the TAP's TDI and TDO pins. Accordingly, such serial-shift is controlled by internal states of the TAP Controller so that the TDO drive is enabled only during the Shift-IR or the Shift-DR states of the TAP Finite State Machine (FSM). At all other times, the TDO output is disabled by forcing it into an inactive or high-impedance state. Either a specialized version of the TAP controller or an Addressable TAP Linking (ATL) circuit may be employed to implement the multi-drop bus configuration 300 of FIG. 3. Such an ATL circuit is described in co-pending U.S. Patent Application No. 60/303,052 filed Jul. 5, 2001 entitled METHOD AND APPARATUS FOR OPTIMIZED PARALLEL TESTING AND ACCESS OF ELECTRONIC CIRCUITS.
An external test controller can be connected to the TDI, TDO, TMS, TCK, and TRSTN lines of the respective IEEE 1149.1 bus in the daisy chained or multi-drop configurations 200 and 300. The external test controller can then communicate with the respective Units Under Test (UUTs) 202.1-202.n or 302.1-302.n using the IEEE 1149.1 bus protocol. These bus configurations 200 and 300 are commonly used in production manufacturing of electronic systems, in which the external test controller is typcially some form of Automatic Test Equipment (ATE) such as an In-Circuit Tester (ICT) or a Personal Computer (PC) based boundary scan tool.
There is a need for embedding Built-In Self-Test (BIST) capability within a system to be tested, on one or more PCBs of the system to be tested, and/or on one or more ICs of the system to be tested. Such embedded BIST capability would allow circuitry resident within the system to apply scan vector sequences that would otherwise be applied by an external test controller. Further, such embedded BIST capability would enable tests to be readily performed either remotely or in the field. For example, such testing may be performed automatically at system power-up or by invoking the embedded BIST circuitry at some other time.
FIG. 4 depicts a conventional configuration 400 for providing embedded BIST capability in electronic systems. The BIST configuration 400 comprises an architecture designed around a general-purpose microprocessor 402 and a data conversion circuit 404 that converts between the parallel data/protocol of the microprocessor 402 and the serial scan protocol (e.g., the IEEE 1149.1 protocol) of the UUT. As shown in FIG. 4, both Read-Only Memory (ROM) 406 and Random Access Memory (RAM) 408 are connected to a bus 410 of the microprocessor 402. The ROM 406 stores program code and the RAM 408 stores data used when the microprocessor 402 executes the stored programs.
The embedded BIST configuration 400 further includes interface logic 412 connected between the microprocessor 402 and the parallel/serial protocol converter circuit 404 to match the address and control signals of the microprocessor 402 to those of the converter circuit 404. The parallel protocol/data of the microprocessor 402 are converted to the inputs and outputs forming the IEEE 1149.1 bus 414 by the parallel/serial converter 404. The IEEE 1149.1 bus 414 may then be employed to drive a respective IEEE 1149.1 bus on a PCB or within an IEEE 1149.1 bus configuration such as the daisy chained configuration 200 (see FIG. 2) or the multi-drop configuration 300 (see FIG. 3). Moreover, the embedded BIST configuration 400 includes an external connector 416 that bypasses the parallel/serial protocol converter circuit 404 and enables an external test controller 407 to be connected in place of the data conversion circuit 404. When the external test controller 407 is connected in this manner, an OE signal operates to disable the parallel/serial protocol converter circuit 404 from controlling the IEEE 1149.1 bus 414, thereby allowing the external test controller 407 to control the IEEE 1149.1 bus 414.
As described above, the conventional embedded BIST configuration 400 includes the microprocessor 402, non-volatile storage in the form of the ROM 406, and read/write storage in the form of the RAM 408. For such a microprocessor-based approach, a user (i.e., a human operator) normally writes program code (e.g., C code) and compiles and links the code with a library of scan test functions. The linked code resides in the ROM 406 (which also includes the scan vector data) and is executed by the microprocessor 402 to apply and evaluate the scan vectors. The RAM 408 is employed for temporary storage during various microprocessor operations such as comparing actual scan-out data with expected scan-out data.
As a result, the conventional configuration 400 for providing embedded BIST capability requires customization of the embedded test solution for each application. Specifically, the program code is developed and debugged for each specific system. In addition, the scan vectors that are normally applied by the external test controller are converted to operate with the embedded test software, which often comprises a different test application environment than that used by the external test controller (i.e., different processor architecture, different operating system, and different software drivers). This requires extra work in addition to test development and debug with the external test controller and therefore adds to the total system cost and complexity.
Moreover, in the conventional embedded BIST configuration 400, the microprocessor 402 is often shared or re-used as the test processor. This approach is intended to save costs by not requiring a separate dedicated processor for use as the embedded test controller. However, the microprocessor 402 and any other support circuitry the microprocessor 402 requires typically cannot be placed in the scan chain(s) of the system during embedded testing because this circuitry is employed to apply and analyze the embedded tests. Accordingly, the fault coverage of the system during embedded testing is reduced because the entire microprocessor infrastructure of the system is not part of the embedded test. Further, a significant portion of the system (e.g., the microprocessor 402 and all its support circuitry) must be free from defects in order to test the remainder of the system. So, although this approach may reduce circuit costs for embedded BIST implementation, test costs may increase. For example, the microprocessor infrastructure of the system may require a separate test methodology and development effort, and may be unable to take advantage of the structured scan methodologies of the remainder of the system.
The need for embedded BIST capabilities in PCBs and systems has grown considerably as the designs of ICs, PCBs, and systems have become more complex. Advances in electronic designs have enabled new product capabilities in the areas of, e.g., telecommunications and information technologies. Such advances have resulted in a growing need for high quality built-in testing and ISC of programmable logic (e.g., CPLDs and FPGAs). Further, increased market demand for such products and increased competition in the market place continue to place pressure on manufacturers of electronic systems to reduce costs and improve time to market. Accordingly, new techniques that both reduce costs and minimize the time required for embedded BIST and ISC of PCBs and systems are needed.